# Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture

## TL;DR

This paper introduces a secure SRAM-PUF design using ECDSA to enhance cybersecurity and reduce error rates in device authentication.

## Contribution

A novel ECDSA-based SRAM-PUF with a universal architecture for efficient scalar multiplication operations is proposed.

## Key findings

- The proposed SRAM-PUF achieves a bit error rate of 2.7×10−10.
- The design shows improved area–time performance with 3902 slices and 6.615 μs ECDSM latency.
- A universal architecture for ECSM and ECDSM operations saves hardware resources.

## Abstract

Physically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning. The SRAM-PUF, characterized by its simple structure and ease of implementation in various scenarios, has gained widespread usage. The soft-decision Reed–Muller (RM) code, an error correction code, is commonly employed in these designs. This paper introduces the design of an RM code soft-decision attack algorithm to reveal its potential security risks. To address this problem, we propose a soft-decision SRAM-PUF structure based on the elliptic curve digital signature algorithm (ECDSA). To improve the processing speed of the proposed secure SRAM-PUF, we propose a custom ECDSA scheme. Further, we also propose a universal architecture for the critical operations in ECDSA, elliptic curve scalar multiplication (ECSM), and elliptic curve double scalar multiplication (ECDSM) based on the differential addition chain (DAC). For ECSMs, iterations can be performed directly; for ECDSMs, a two-dimensional DAC is constructed through precomputation, followed by iterations. Moreover, due to the high similarity of ECSM and ECDSM data paths, this universal architecture saves hardware resources. Our design is implemented on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) using a Xilinx Virtex-7 and an TSMC 40 nm process. Compared to existing research, our design exhibits a lower bit error rate (2.7×10−10) and better area–time performance (3902 slices, 6.615 μs ECDSM latency).