# A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

## TL;DR

This paper introduces a new method to reduce program disturbance in 3D NAND flash memory by using a GIDL pre-charge technique.

## Contribution

The novel contribution is a channel preparation scheme using GIDL pre-charge to suppress program disturbance without modifying NAND structure or Vpass bias.

## Key findings

- The GIDL pre-charge method effectively enhances unselected channel potential.
- The technique suppresses program disturbance and increases the pass disturb window.
- Results are validated using TCAD simulations and real silicon data.

## Abstract

The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction of program disturbance is that the operational Vpass during the program’s performance cannot be too high or too low. For instance, the 3D NAND program’s operation string needs a lower Vpass bias to suppress unselected WL Vpass bias-induced Fowler–Nordheim tunneling (FN tunneling), but for the inhibited string, the unselected WL needs a higher Vpass bias to suppress selected WL program bias (Vpgm)-induced FN tunneling. In this paper, a systematical insight into the relationship between the channel potential and channel electron density is given. Based on this intensive investigation, we studied a novel channel preparation scheme using “Gate-induced drain leakage (GIDL) pre-charge”. Our methodology does not require the introduction of any new structures in 3D NAND, or changes in the operational Vpass bias. Instead, the potential on the unselected channel is enhanced by exploiting the holes generated by the GIDL operation effectively, leading to significantly suppressed program disturbance and a larger pass disturb window. To validate the effectiveness of the “GIDL pre-charge” method, TCAD simulation and real silicon data are used.