A Hardware-Based Multi-Stage Dynamic Power Management Architecture for Autonomous Low-Light Operation

TL;DR

This paper presents a hardware-based multi-stage dynamic power management system that drastically reduces quiescent current in autonomous sensor nodes, enhancing low-light operation efficiency.

Contribution

It introduces a novel hardware architecture with complete power gating and a specialized latch circuit to minimize energy consumption in low-light environments.

Findings

Achieves a quiescent drain of 452nA, significantly lower than traditional methods.

Demonstrates improved energy efficiency over software-based sleep modes.

Enables longer autonomous operation in photovoltaic-powered sensor networks.

Abstract

The advance of autonomous Smart Sensor Networks and embedded systems for the Internet of Things, powered by photovoltaic energy harvesting, is severely limited by energy efficiency, especially in low-light environments. While Dynamic Power Management is essential for energy conservation, conventional software-based techniques that rely on processor-managed low-power states incur a persistent quiescent current drain. This current becomes the dominant energy sink in energy-scarce conditions, limiting autonomy. The work of this paper addresses this limitation by introducing a robust, hardware-orchestrated dynamic power management architecture that improves existing configurations for battery-based sensor nodes. The proposed architecture achieves a minimal quiescent drain of 452nA, by completely power-gating the microcontroller and all non-essential peripherals, with wake-up orchestrated by an ultra-low-power PMIC, RTC and a novel latch circuit developed specifically for this work. Our evaluation demonstrates that the dynamic power management architecture is significantly more efficient than traditional software-based sleep modes.