Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations

TL;DR

This paper introduces a novel input transformation technique for arithmetic multipliers that mitigates NBTI aging effects, extending IC lifetime with minimal overhead, especially in AI accelerators.

Contribution

It proposes a sign-invariance based input transformation method to reduce aging in multipliers, integrated into systolic arrays for AI accelerators.

Findings

Enhanced lifetime of multipliers under NBTI aging

Negligible area and delay overheads

Effective in high-throughput AI accelerators

Abstract

Hardware aging poses a significant challenge for integrated circuits (ICs), leading to performance degradation and eventual failure. In this work, we focus on the aging of arithmetic multipliers, which are a cornerstone of modern computing systems including in CPUs, GPUs, and FPGAs, as well as AI accelerators like systolic arrays. In particular, AI workloads, which rely predominantly on multiplications, can accelerate Negative Bias Temperature Instability (NBTI) effects in multipliers. This paper presents a novel aging mitigation technique that leverages the signinvariance property of multiplication. By selectively applying 2s complement transformations to inputs, the method redistributes stress across transistors, reducing the effects of NBTI aging. The proposed method is also integrated into systolic arrays, a common AI accelerator, to demonstrate its efficiency in a high-throughput AI accelerator. Experimental evaluations using Cadence tools show better lifetime compared to natural aging (with no mitigation) baseline, while introducing negligible area and delay overheads.