Debug Like a Human: Scaling LLM-based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing

TL;DR

BluesFL is a novel LLM-based fault localization framework for processor design that uses block-level code slicing and instruction analysis to efficiently identify bugs in large-scale hardware code.

Contribution

It introduces a block-level instruction-oriented slicing algorithm that enables LLMs to mimic human debugging reasoning in processor verification.

Findings

Successfully localized 24 bugs at Top-1 in a real-world RISC-V core.

Achieved 242.9% improvement over state-of-the-art methods.

Average cost of bug localization is only $0.257.

Abstract

Fault localization in modern processor design code is a critical yet time-consuming step during processor verification. While recent advances in LLM-based techniques for module-level hardware design have shown promising results, automatically localizing bugs in large-scale, project-level processor designs remains challenging. In this paper, we present BluesFL, a novel block-level LLM-based fault localization framework for processor designs. Inspired by the way engineers debug processors, we first propose a dataflow-based code blockization approach to guide LLMs to focus on critical local code context. We further propose a Block-Level Instruction-Oriented Slicing (Blues) algorithm that enables LLMs to mimic human reasoning by analyzing instruction execution paths and processor states. We evaluate BluesFL on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code. Experimental results demonstrate that BluesFL correctly localizes 24 bugs at Top-1, achieving 242.9% improvement over the existing state-of-the-art (7 bugs). Cost analysis shows that BluesFL requires an average of only $0.257 to localize a single bug.