Triple-Hoisted Baby-Step Giant-Step Linear Transformation over CKKS Homomorphic Encryption and Hardware Accelerator

TL;DR

This paper introduces a novel triple-hoisted baby-step giant-step algorithm and FPGA-based hardware accelerator to efficiently perform linear transformations over CKKS homomorphic encryption, significantly reducing memory access and latency.

Contribution

It proposes a new algorithm and hardware design that together decrease ciphertext rotations, memory access, and computation latency for HE-based linear transformations.

Findings

Reduces off-chip memory access by 2.9x compared to prior designs.

Achieves a 5.8x reduction in computational latency on FPGA.

Decreases ciphertext rotations needed for CKKS linear transformation.

Abstract

Computations can be directly carried out over ciphertexts using homomorphic encryption (HE), which is indispensable for privacy-preserving cloud computing. Linear transformation is widely used in neural networks, including large language models. However, the implementation of linear transformation over HE requires a large number of ciphertext rotations, which incur significant memory and hardware overhead despite existing simplification techniques. This paper proposes a triple-hoisted baby-step giant-step algorithm that decomposes the baby step further to substantially reduce the number of ciphertext rotations needed for the CKKS HE evaluation of linear transformation. Moreover, to reduce off-chip memory access, which contributes to the majority of the latency, a memory-optimized data path is proposed by partitioning the algorithm into multiple phases. Furthermore, an efficient FPGA-based hardware accelerator with an optimized permutation circuit for message routing is designed for the proposed scheme. For a set of typical parameters, the proposed design reduces the off-chip memory access by 2.9x compared to the best prior design. Synthesized for Xilinx Virtex UltraScale+ devices, the proposed design achieves a 5.8x reduction in computational latency compared with the baseline design.