Demonstration of transport in an ion trap design for two-dimensional lattices

TL;DR

This paper demonstrates a novel ion trap chip design enabling control of ion spacing via dc voltages, facilitating scalable two-dimensional quantum lattice architectures.

Contribution

It introduces a new ion trap chip design that allows radial ion distance tuning solely with dc voltages, simplifying control in quantum lattice systems.

Findings

Successfully demonstrated dc-controlled radial transport of a single ion.

Measured stray fields and ion heating rates in the trap center.

Presented a multi-metal layer fabrication path for scalability.

Abstract

Microfabricated ion trap chips are at the core of some of the most advanced quantum computers. How a large number of ions is arranged and controlled on an ion trap chip depends on the chosen trap architecture. One such architecture is the quantum spring array (QSA). In the QSA architecture, ion chains are arranged in a two-dimensional lattice and interact with ion chains in neighboring sites in the radial and axial directions of the respective chain. This interaction, or coupling, is mediated by the Coulomb force while keeping ions in separate trapping sites, and scales inversely with the third power of the separation. The capability to control the distance between ions in the lattice is thus essential. In previous works, the radial separation between ions was tuned by controlling the rf pseudo-potential, which revealed to be experimentally challenging to realize while maintaining low heating rates. In this work, we present an ion trap chip design that allows tuning of the radial distance between ions using only dc voltages. The radial transport is executed between different interaction zones, designated for quantum operations, through specifically designed transition zones. A prototype of this type of ion trap chip was microfabricated on fused silica substrate. Its functionality is characterized by demonstrating dc-controlled radial transport of a single ion through a transition zone and measuring stray fields and ion heating rates in the center of the trap. Moreover, the fabrication of a multi-metal layer version of such a trap is presented as a scaling path for the presented chip design.