ADS-IMC: Accelerating Data Sorting with In-Memory Computation

TL;DR

This paper presents a novel in-memory sorting architecture using 6T SRAM to significantly reduce latency and energy overheads associated with traditional data transfer-based sorting methods.

Contribution

It introduces the first in-memory sorting architecture with 6T SRAM, eliminating off-chip data transfer and achieving 3.4x latency reduction over memristor-based IMC sorting.

Findings

Achieves 3.4x latency reduction compared to memristor-based IMC sorting.

Operates directly within SRAM memory fabric, reducing data movement overhead.

First exploration of in-memory sorting using 6T SRAM.

Abstract

Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This conventional approach incurs substantial latency and energy overheads due to the extensive data movement between memory and processing components. To mitigate these overheads, this paper introduces novel architectures for executing sorting operations directly within the memory fabric, eliminating the need for off-chip data transfer. To our knowledge, this work represents the first exploration of in-memory sorting using 6T SRAM. The proposed architecture is designed to operate on data represented in the standard weighted binary radix format commonly used in digital systems. The proposed architecture achieves a significant 3.4x reduction in latency compared to memristor-based IMC sorting.