Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip

TL;DR

This paper introduces a scalable, energy-efficient neuromorphic computing architecture using clockless FPGA-based digital circuits that emulate spiking neural networks for machine learning tasks.

Contribution

It demonstrates a novel approach to neuromorphic computing on reconfigurable digital hardware, bridging digital and analog paradigms without specialized hardware.

Findings

Achieved competitive audio classification performance with spike-based encoding.

Significantly reduced power consumption compared to traditional digital systems.

Proved clockless digital hardware as a viable platform for neuromorphic computing.

Abstract

We propose a scalable neuromorphic architecture based on spiking dynamics emerging from the autonomous time-continuous evolution of clockless (asynchronous) digital circuits. Implemented on commercially available field-programmable gate arrays (FPGAs), our system implements networks of interacting Boolean spiking neurons with configurable excitatory and inhibitory synaptic weights. A complete processing pipeline enables efficient handling of spike-encoded data for solving machine-learning tasks. We demonstrate competitive performance for an audio classification task with spike-based encoding and high-speed processing. Power consumption is significantly lower than traditional digital implementations; this makes our approach an efficient alternative that bridges the gap to dedicated analog neuromorphic systems without the need for specialized hardware design. More generally, our approach establishes clockless digital hardware as a viable platform for neuromorphic computing. It paves the way for reconfigurable chips to be turned into energy-efficient quasi-analog neuromorphic processors.