Fault tolerance estimation in digital circuits with visualised generative networks

TL;DR

This paper introduces a novel numerical method using generative networks to estimate fault tolerance in digital circuits by analyzing deviations in expected output currents under various failure modes.

Contribution

It presents a new approach combining GAN-based sampling with complex variable analysis to evaluate circuit robustness against different failure modes.

Findings

Method effectively estimates fault tolerance in digital circuits.

Analyzes impact of failure modes on logical device performance.

Provides a framework for robustness evaluation using generative networks.

Abstract

We propose a new numerical method to estimate the fault tolerance of failure modes in digital circuit structures with a generative network sampling technique. From a random input of generated bitwise configurations of ideally digitalised analog currents in the digital circuit design with classical logical gates, expected output currents are compared to the realistic signals of a numerical experiment at the discriminator part of the Generative Adversarial Network (GAN) to calculate the deviation from ideal digital electronic signals, including various error modes, such as missing or interchanged logical devices. From the present analysis of a representation of the GAN in terms of complex variables, it is possible to evaluate the robustness in electronic designs by differentiating the impact of failure modes associated with different classical logical elements in the circuit.