Time Domain Near Memory Computing Engine
Sarthak Antal, Steve Enosh

TL;DR
This paper introduces a novel time-domain near-memory computing engine for low-precision MAC operations, enhancing energy efficiency and scalability in AI workloads.
Contribution
It proposes a time-domain architecture that performs multiplication in the time domain, reducing overhead and improving energy efficiency compared to traditional analog approaches.
Findings
Achieved 40 MHz operation at 1 V with 42 μW power consumption.
Demonstrated energy efficiency of 7.62 TOPS/W in a 4x4 MAC prototype.
Compared delay-cell and counter-based accumulation schemes for trade-offs.
Abstract
The increasing computational demand of AI workloads has intensified the need for energy-efficient in-memory and near-memory computing architectures, particularly because data movement often consumes significantly more energy than computation itself. While fully digital architectures provide robust scalability and support higher-resolution computation, analog in-memory computing has demonstrated improved energy efficiency for low-precision workloads. However, its reliance on peripheral DACs and ADCs introduces additional power, area, and design overhead. To address these challenges, this work presents a time-domain near-memory computing architecture for low-precision multiply-and-accumulate (MAC) operations. In the proposed approach, digital weight bits stored in SRAM are converted using a current-steering DAC, while the digital input vector is encoded by an N-pulse generator. This…
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