On-chip 1 TOPS Hyperdimensional Photonic Tensor Core using a WDM Silicon Photonic Coherent Crossbar

TL;DR

This paper presents a silicon photonic tensor core achieving nearly 1 TOPS for AI tasks, utilizing a WDM crossbar architecture that enhances scalability and efficiency in photonic computing.

Contribution

The work introduces a novel on-chip photonic tensor core architecture with WDM multiplexing, demonstrating high-speed tensor operations and potential for scalable photonic AI accelerators.

Findings

Achieved 0.96 TOPS tensor core operation with 4-channel WDM silicon photonics.

Demonstrated 93.3% accuracy on Iris dataset classification at high data rates.

Showed that WDM integration reduces laser power and enhances scalability.

Abstract

We demonstrate an on-chip 0.96 TOPS hyperdimensional photonic tensor core by utilizing a time-spacewavelength multiplexed silicon photonic Crossbar (Xbar). The novel architecture relies on serializing the large matrix-vector or tensor-vector products by unfolding multiply and accumulation operations over time domain, while simultaneously distributing the computational workload over different spatial and wavelength channels. We experimentally demonstrate the operation of a 4-channel 2-input TSWDM Xbar that incorporates 56 GHz electroabsorption modulators (EAMs) and 4-channel integrated multiplexing stages. Its successful operation as a 4x2x1 tensorvector multiplication unit demonstrated an average error of 3.9%. Its performance as a photonic AI accelerator was also evaluated in the classification task of the Iris dataset, presenting experimental accuracies of 93.3% at data rates between 4x10 and 4x30 GBd, reaching 83.3% when the data rate increases to 4x60 GBd. Finally, we discuss the TSWDM Xbar scalability potential, revealing that the inclusion of a WDM scheme in the SDM architecture reduces the operating laser power, feasibly boosting the potential of constructing photonic accelerators with computational throughput in the POPS regime.