A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine

TL;DR

This paper introduces SACHI, an all-digital, reuse-aware Ising machine leveraging CPU cache SRAMs for efficient, reliable optimization, achieving significant performance and energy improvements over prior approaches.

Contribution

SACHI is a novel architecture that repurposes CPU cache SRAMs for all-digital Ising acceleration, eliminating ADC/DAC reliance and enhancing reliability and efficiency.

Findings

SACHI achieves 300x performance improvement over BRIM.

SACHI reduces energy consumption by 80x compared to prior methods.

Reuse factors up to 4000x observed for various workloads.

Abstract

Recently, nature-inspired computing approaches have gained significant attention for solving difficult optimization problems, particularly through Ising machines for NP-complete applications. Existing Ising accelerators range from quantum and optical annealers to CMOS-based von-Neumann and in-memory architectures. However, many prior designs are specialized accelerators limited to specific problem classes, rely on ADC/DAC circuits, and suffer from reliability challenges due to process-variation-sensitive embedded memory technologies. This paper presents SACHI, an all-digital Ising architecture implemented by repurposing the L1 cache of a CPU using SRAM-based processing-in-memory techniques. SACHI eliminates the need for ADCs/DACs, improves reliability compared to prior approaches such as BRIM, and enables Ising acceleration with minimal hardware overhead integrated into the CPU pipeline. The paper also provides detailed architectural analysis and pseudo-code for the proposed algorithms. The key contributions of SACHI are: (i) tight integration of the accelerator with the CPU pipeline, (ii) reuse of existing cache hardware for acceleration, (iii) higher parallelism enabled through reuse-aware computation, and (iv) improved performance and energy efficiency for large-scale, high-precision optimization problems using novel compute and mapping strategies. Compared to BRIM, SACHI achieves 300x performance improvement and 80x energy reduction across applications including asset allocation, molecular dynamics, image segmentation, and traveling salesman problems. Additionally, reuse factors up to 4000x are observed for several workloads. This work demonstrates that reliable and efficient all-digital Ising acceleration can be achieved using commodity SRAM structures tightly integrated with general-purpose processors.