Controllable Quantum Memory Capacity in Quantum Reservoir Networks with Tunable partial-SWAPs

TL;DR

This paper introduces a tunable partial-SWAP mechanism for quantum reservoir networks, enabling direct control over memory capacity on gate-based quantum processors, validated through simulations and IBM QPU experiments.

Contribution

It presents a hardware-realizable, controllable mechanism for quantum memory capacity in reservoir networks, advancing recurrent quantum architectures.

Findings

The tunable partial-SWAP allows direct control of memory dissipation.

Validation on IBM QPUs shows effective memory management.

Simulations confirm the mechanism's theoretical predictions.

Abstract

In the field of quantum reservoir computing (QRC), many different computational models and architectures have been proposed. From these models, we identify feedback-based models -- which use a feedback mechanism to re-embed classical measurements from the QRC -- and recurrent models -- which use a multi-register approach with memory and readout qubits -- as the two major competing architectures that have been discussed and validated on hardware. In this paper, we advance upon the recurrent architectures, which employ a two register approach to endow the QRC with a fading memory. While these approaches have been validated on hardware and have demonstrated great real-world performance on noisy-intermediate-scale-quantum (NISQ) quantum processing units (QPUs), the exact mechanism through which the memory capacity arises is not completely understood or fully controllable. With this, we augment the recurrent approaches and present a hardware-realizable mechanism, which we call a tunable partial-SWAP, that allows for the direct control of the rate of memory dissipation from a QRN implemented on a gate-based QPU. The theory behind this mechanism is discussed in terms of a controlled amplitude-damping channel and validation experiments using a randomized short-term memory capacity (STMC) recall benchmark and the NARMA-5 dataset are conducted using simulation and IBM QPUs, respectively.