Understanding oxide-thickness-dependent variability in dense Si-MOS quantum dot arrays

TL;DR

This study examines how oxide thickness affects uniformity in dense silicon quantum dot arrays, identifying an optimal oxide thickness to minimize variability for scalable quantum computing.

Contribution

It provides the first comprehensive statistical analysis of oxide-thickness effects on quantum dot uniformity in a large CMOS-fabricated array.

Findings

Optimal SiO2 thickness of 17 nm reduces threshold voltage variability below 63 mV

Multiple disorder sources cause non-monotonic oxide-thickness dependencies

Guidelines for scalable silicon spin qubit architecture design are established

Abstract

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.