Rethink the Role of Neural Decoders in Quantum Error Correction

TL;DR

This paper investigates neural decoders for quantum error correction, emphasizing accuracy-latency tradeoffs, and proposes design principles for real-time FPGA deployment with up to 161 qubits.

Contribution

It unifies and redesigns neural decoder architectures, introduces an end-to-end compression pipeline, and offers practical insights for scalable, real-time quantum error correction.

Findings

Data scale impacts decoding performance more than architecture complexity.

Inductive bias is crucial for high decoding accuracy.

INT4 quantization enables meeting microsecond latency on FPGAs.

Abstract

Quantum error correction (QEC) is essential for enabling quantum advantages, with decoding as a central algorithmic primitive. Owing to its importance and intrinsic difficulty, substantial effort has been made to QEC decoder design, among which neural decoders have recently emerged as a promising data-driven paradigm. Despite this progress, practical deployment remains hindered by a fundamental accuracy-latency tradeoff, often on the microsecond timescale. To address this challenge, here we revisit neural decoders for surface-code decoding under explicit accuracy-latency constraints, considering code distances up to d=9 (161 physical qubits). We unify and redesign representative neural decoders into five architectural paradigms and develop an end-to-end compression pipeline to evaluate their deployability and performance on FPGA hardware. Through systematic experiments, we reveal several previously underexplored insights: (i) near-term decoding performance is driven more by data scale than architectural complexity; (ii) appropriate inductive bias is essential for achieving high decoding accuracy; and (iii) INT4 quantization is a prerequisite for meeting microsecond-scale latency requirements on FPGAs. Together, these findings provide concrete guidance toward scalable and real-time neural QEC decoding.