FPGA-Based Hardware Architecture for Contrast Maximization in Event-Based Vision

TL;DR

This paper introduces a novel FPGA hardware architecture that accelerates the Contrast Maximization algorithm for event-based vision, enabling real-time, energy-efficient motion estimation in embedded systems.

Contribution

The paper presents the first hardware design for the CM algorithm, achieving over 200x speedup and demonstrating suitability for real-time embedded event-based vision applications.

Findings

Speed and efficiency improved over CPU and GPU implementations

Achieves over 200 times faster motion parameter estimation

Validated with event-based object tracking application

Abstract

This paper presents a hardware architecture that implements the Contrast Maximization (CM) algorithm in Field-Programmable Gate Array (FPGA) resources for event-based vision systems. CM estimates motion parameters by maximizing the contrast of an Image of Warped Events (IWE) reconstructed from asynchronous event streams. Event-based vision sensors generate sparse data with high temporal resolution and low spatial redundancy, which makes them well suited for hardware processing. The deterministic, massively parallel structure of the FPGA is leveraged to design a deeply pipelined architecture capable of high-throughput, energy-efficient processing suitable for real-time embedded applications. This paper details the hardware modules responsible for event warping, contrast computation, and iterative optimization, discusses key implementation decisions, and presents the hardware-aware optimization method used in the design. Experimental results demonstrate a substantial speed and efficiency improvement over CPU- and GPU-based implementations, with motion parameter estimation executing over 200 times faster. To the best of our knowledge, this is the first hardware architecture enabling acceleration of CM algorithm computations. Its performance is evaluated in terms of processing speed, energy efficiency, and hardware resource utilization. The proposed design is validated using an event-based object tracking application. The results confirm that the architecture provides a solid foundation for real-time motion estimation in high-speed, low-power embedded systems.