31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding

TL;DR

This paper introduces a high-speed, energy-efficient LLM accelerator using ReRAM-on-logic stacking, innovative quantization, and adaptive speculative decoding to significantly improve processing speed and resource utilization.

Contribution

It presents a novel 55nm speculative decoding-based LLM accelerator with ReRAM stacking, outlier-free quantization, and adaptive parallel decoding for enhanced performance.

Findings

Achieves 14.08-to-135.69 tokens/sec processing speed.

Provides 4.46-to-7.17x speedup over vanilla speculative decoding.

Demonstrates high resource and bandwidth utilization.

Abstract

This work presents a 55nm speculative decoding-based LLM accelerator with bumping-based face-to-face ReRAM-on-logic stacking technology. It features a local rotation unit for outlier-free low-bit quantization, a stacking-aware PNM architecture co-designed with blockwise vector quantization to reduce weight EMA overheads, and an adaptive parallel speculative decoding scheme with an out-of-order scheduler for high resource and bandwidth utilization. Our chip achieves 14.08-to-135.69token/s and 4.46-to-7.17x speedup over vanilla speculative decoding.