DART-Q : A Deadline-Driven Framework for Real-Time QLDPC Decoding

TL;DR

DART-Q is a real-time decoding framework for quantum low-density parity-check codes that models workload as deadline-driven queueing, optimizing for timely correction under strict memory and timing constraints.

Contribution

It introduces a queueing-based, deadline-aware decoding framework that evaluates operational viability of QLDPC decoders under realistic constraints.

Findings

Cached-summary state organization reduces SRAM-fit boundary by 4x.

Doubling decoder capacity reduces MissRate from 97.64% to 0.98%.

Relaxing backlog cap increases queued work by 20.1x and latency by 17.6x.

Abstract

Real-time quantum error correction places the classical decoder inside the fault-tolerant control loop under strict timing and memory constraints. For quantum low-density parity-check (QLDPC) codes, practical deployment therefore depends not only on correction performance, but also on timely decoding under deadlines, finite on-chip memory, and time-varying load. However, existing decoder studies primarily emphasize correction performance without exposing operational viability under these constraints. We present DART-Q, a real-time QLDPC decoding framework that treats windowed workloads as discrete arrival, queueing, service, and completion events. DART-Q models each decode request as a deadline-driven online service job with queueing and non-preemptive Earliest Deadline First scheduling. It supports configurable admission control, service times, and bounded rescue policies. Through controlled studies of the SRAM-fit transition, tail latency, overload, and a capacity-scaling extension, DART-Q isolates the effects of memory pressure, rescue selectivity, admission control, and pooled service capacity on timely decoding. Our results show that real-time decoder viability is governed by state organization, overload policy, and service capacity. A cached-summary state organization lowers the SRAM-fit boundary by 4x relative to an edge-centric baseline. Under overload, relaxing the backlog cap increases queued work by approximately 20.1x and worsens p99 latency by approximately 17.6x, with little gain in useful throughput. In contrast, doubling decoder capacity reduces the MissRate from 97.64% to 0.98% and improves p99 latency from 3.861ms to 10$\mu$s. These results position DART-Q as a framework for exposing the regime changes that determine real-time QLDPC decoder viability under deadlines, finite memory, and time-varying load.