Low-Complexity Beamspace Channel Denoiser for mmWave Massive MIMO with Low-Resolution ADCs

TL;DR

This paper introduces a low-complexity beamspace channel denoising algorithm for mmWave massive MIMO systems with low-resolution ADCs, leveraging sparsity and Bayesian hypothesis testing.

Contribution

It proposes a computationally efficient denoising method with a hardware-friendly VLSI architecture, enabling practical deployment in large-scale antenna systems.

Findings

Achieves near-optimal denoising performance with reduced complexity

Develops a hardware-efficient FPGA implementation with lower latency

Demonstrates sublinear scaling with the number of antennas

Abstract

In this paper, we propose a low-complexity beamspace channel denoising algorithm for millimeter-wave (mmWave) massive multi-input multi-output (MIMO) systems with low-resolution analog-to-digital converters (ADCs). The proposed method exploits the inherent sparsity of mmWave channels in the beamspace domain and formulates the denoising problem as a Bayesian binary hypothesis testing under a Bernoulli-complex Gaussian prior. To capture the distortion induced by low-resolution ADCs in a complexity-efficient manner, thermal noise and quantization noise are jointly modeled as a composite noise. Based on this modeling, a closed-form threshold value and a hard-thresholding-based denoising rule are derived to distinguish signal-dominant and noise-dominant components. The resulting algorithm avoids computationally intensive operations such as matrix inversion, iterative optimization, and parameter searching, and achieves near-linear computational complexity with respect to the number of antennas. Furthermore, a hardware-efficient very large-scale integration (VLSI) architecture is developed to enable practical deployment of the proposed algorithm, and is implemented on an AMD-Xilinx Kintex UltraScale+ KCU116 FPGA platform. The design incorporates hardware-aware simplifications and an efficient processing structure, leading to significantly lower latency and reduced hardware resource utilization compared to existing hardware implementations, along with sublinear scaling as the number of antennas increases. Extensive simulation results demonstrate that the proposed method achieves performance comparable to computationally intensive existing approaches while significantly reducing computational complexity.