A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core

TL;DR

This paper introduces a runtime reconfigurable multiplier architecture for RISC-V cores that enhances energy efficiency in neural network inference by supporting adaptable accuracy levels and reducing power consumption.

Contribution

It presents a novel multiplier design enabling fine-grained energy-accuracy trade-offs, integrated into RISC-V for improved edge AI performance.

Findings

Achieves 44%-52% power reduction in exact mode.

Attains up to 63% energy savings on error-tolerant workloads.

Maintains 1.89 DMIPS/MHz performance with energy-efficient operation.

Abstract

Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained embedded devices, where the limited available energy poses a significant challenge for efficient inference. This paper presents a runtime reconfigurable multiplier architecture integrated into the RISC-V core, targeting energy efficient neural network inference and edge AI applications. The proposed multiplier supports adaptability for exact and approximate computation with multiple configurable accuracy levels via a dedicated mulscr, enabling fine-grained energy accuracy control within a standard processor pipeline. The proposed design achieves 44%-52% and 62%-68% power reduction in exact and approximate modes respectively, while maintaining the computational performance of 1.89 DMIPS/MHz. Evaluations on error-tolerant workloads including 2d convolution and matrix multiplication demonstrate up to 63% reduction in energy consumption, with the proposed design achieving 1.21 pJ/instruction for matrix multiplication, confirming its effectiveness for energy-constrained edge AI deployments.