Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference

TL;DR

This paper presents a multi-objective Bayesian Optimization framework for designing crossbar-based CIM accelerators, optimizing hardware and algorithm parameters for efficient DNN inference with high-dimensional search spaces.

Contribution

It introduces a holistic BO approach that handles high-dimensional, large-scale design spaces for CIM hardware, improving efficiency metrics while maintaining accuracy.

Findings

Achieves 91.72% and 57.2% accuracy on different DNN tasks.

Reduces chip area by up to 65.52%.

Improves energy efficiency and latency significantly.

Abstract

Leveraging the high density and energy efficiency of Compute-In-Memory (CIM) crossbar-based Deep Neural Network (DNN) accelerators requires optimal Design Space Exploration (DSE), which becomes increasingly challenging as complex models for advanced AI workloads expand the highly non-convex design space. Moreover, heterogeneous layer workloads (e.g., memory- vs. compute-bound) and learning representations make layer-wise NN parameter allocation beneficial for efficiency but severely exacerbate the design space complexity by expanding the number of parameters to be tuned for simultaneous multi-objective optimization. Among existing DSE approaches, multi-objective Bayesian Optimization (BO) is promising, as it explores high-quality design solutions while querying costly CIM simulators selectively. In this work, we propose a multi-objective BO framework that holistically co-optimizes hardware and algorithm parameters of a CIM crossbar-based hardware accelerator for various DNN inference tasks. Depending on NN model depth, our framework handles high-dimensional design spaces (with $26$ and $50$ dimensions) and extremely large search complexities on the order of $O(10^{12})$ and $O(10^{27})$ for VGG8/CIFAR-10 and VGG16/Tiny-ImageNet-200. Our method attains $91.72 \%$ and $57.2 \%$ accuracy, respectively, comparable to baseline designs, while improving chip area ($65.52 \%$ and $50.7 \%$), read latency ($9.52 \%$ and $13.27 \%$), read dynamic energy ($31.23 \%$ and $52.07 \%$) and increasing memory utilization ($13.41 \%$ and $2.67 \%$).