A Hardware-aware Hopfield Network with a Nonlinear Memristor Array for Robust Associative Memory with Superlinear Capacity

TL;DR

This paper presents a hardware-aware Hopfield network utilizing nonlinear memristors to significantly enhance memory capacity and robustness for associative memory tasks, surpassing classical limits.

Contribution

The introduction of a memristor-based nonlinear energy landscape engineering enables scalable, high-capacity, hardware-efficient associative memory with robust performance.

Findings

Memory capacity far exceeds classical limit (K ~ 0.14N)

Reliable pattern reconstruction demonstrated with 25x25 memristor array

Empirical capacity scaling of K ~ 0.3 x N^1.2 in high-dimensional data

Abstract

Associative memory retrieves complete patterns from partial or corrupted inputs and constitutes a primitive form of generative inference. Classical Hopfield networks (CHN) provide a canonical framework for associative memory but suffer from limited memory capacity. Recently, modern Hopfield networks (MHN) were introduced to achieve higher capacity by using explicit pattern-wise storage and neurons with the softmax activation function, which makes the MHN vulnerable to noise and the hardware implementation complicated due to its network size varying with the number of stored patterns. Here, we introduce a hardware-aware Hopfield network (HHN), in which the intrinsic nonlinear current-voltage characteristics of a charge-trap memristor are leveraged to engineer the energy landscape of the HN, increasing the memory capacity. Using a 25 x 25 nonlinear memristor array, we demonstrate reliable reconstruction of corrupted patterns with memory capacity far exceeding the classical limit (K ~ 0.14N, where N is the number of neurons). The HHN preserves Hopfield-type energy-minimization dynamics and remains robust to synaptic conductance noise. Large-scale simulations on high-dimensional image data reveal an empirical memory capacity scaling of K ~ 0.3 x N^1.2 under a fixed synaptic budget. These results establish HHN as a scalable hardware-native architecture for low-power associative memory and generative inference.