A 0.08 pJ/bit 56 GBaud Monolithic Optical Receiver Front End for IMDD Photonic Links

TL;DR

This paper reports the design and fabrication of a low-power, high-bandwidth monolithic optical receiver front end supporting 56 Gbaud IMDD transceivers, achieving 28.9 GHz bandwidth with minimal noise and power consumption.

Contribution

It introduces a monolithic, layout-driven design approach for an optical receiver front end with optimized transistor configurations, enabling high bandwidth and low noise at ultra-low power.

Findings

Achieved 28.9 GHz analog bandwidth with 61.7 dBΩ gain.

Supported 64 GBaud data rate with 0.08 pJ/bit energy efficiency.

Consumed only 9.22 mW power from 1.2 V supply.

Abstract

We present the design, fabrication, and measurement of a monolithically integrated optical receiver analog front end, where low power operation is a primary consideration with a goal of supporting 56 Gbaud intensity modulated direct detect transceivers. The need for low-power consumption and low-noise operation motivates a monolithic, layout driven design approach which begins with circuit topology selection and analysis. Various transistor unit cell layout configurations are explored, minimizing parasitics, enabling wide analog bandwidth and reduced input referred noise. The post-layout analog front end achieves a 28.9 GHz bandwidth with a low-frequency gain of 61.7 dB{\Omega}. This circuit was designed within the GlobalFoundries FotonixTM monolithic silicon photonics platform. The fabricated device is characterized by its DC operation, noise characteristics, and time domain behavior. The final design was validated by on-off keyed and PAM-4 electrical eye diagram measurements to 64 GBaud, consuming 9.22 mW of power from a 1.2 V supply with less than 737 nA RMS integrated input referred noise current and 0.08 pJ/bit.