Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification
Vaisakh Naduvodi Viswambharan, Keerthan Kopparam Radhakrishna, Deepak Narayan Gadde, Aman Kumar

TL;DR
This paper introduces a verification-centric Knowledge Graph that enhances the synthesis of SystemVerilog Assertions from natural language specifications, improving grounding, syntax correctness, and coverage in formal verification workflows.
Contribution
It presents a novel Knowledge Graph approach that integrates structured IRs and feedback to improve assertion generation and refinement in formal verification.
Findings
KG-based context retrieval improves specification-to-RTL grounding.
Consistently produces compilable SVAs with low syntax-repair overhead.
Achieves formal coverage from 78.5% to 99.4% across benchmarks.
Abstract
Recent advances in Large Language Models (LLMs) have enabled workflows that generate SystemVerilog Assertions (SVAs) from natural-language specifications, with the potential to accelerate Formal Verification (FV). However, high-quality assertion synthesis remains challenging because specifications are often ambiguous or incomplete and critical micro-architectural details reside in the Register Transfer Level (RTL). Many existing approaches treat the specification and RTL as loosely structured text, which weakens specification-to-RTL grounding and leads to semantic mismatches and frequent syntax failures during formal parsing and elaboration. This work addresses these limitations with a verification-centric Knowledge Graph (KG) constructed from structured Intermediate Representations (IRs) extracted from the specification, RTL, and formal-tool feedback, including syntax diagnostics,…
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