LLM-Driven Design Space Exploration of FPGA-based Accelerators
Vinamra Sharma, Xingjian Fu, Jude Haris, Jos\'e Cano

TL;DR
This paper introduces SECDA-DSE, a novel framework integrating Large Language Models into FPGA accelerator design space exploration, automating configuration generation and reasoning to improve efficiency and effectiveness.
Contribution
The work presents a new LLM-augmented DSE framework for FPGA accelerators, combining structured exploration, reasoning-guided search, and reinforcement learning for continuous improvement.
Findings
SECDA-DSE can generate FPGA accelerator configurations meeting timing and resource constraints.
The framework demonstrates feasibility through initial synthesis-based evaluation on Zynq-7000 FPGA.
LLMs effectively assist in reasoning-guided exploration of complex hardware design spaces.
Abstract
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that…
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