Surface-Code Thresholds and Qubit Footprints in Shuttling-Based Spin-Qubit Railways

TL;DR

This paper proposes a fault-tolerant surface code implementation on a silicon spin-qubit railway, showing improved thresholds by shuttling check qubits and tailoring codes to noise bias, enabling hardware-efficient quantum error correction.

Contribution

It introduces a novel mapping of surface codes onto a shuttling-based architecture and demonstrates threshold improvements by exploiting noise bias and shuttling check qubits.

Findings

Shuttling check qubits enhances system thresholds.

Non-CSS XZZX surface code outperforms CSS variants under dephasing bias.

A distance 7 code can achieve a Megaquop footprint at a physical error rate of 10^{-3}.

Abstract

We present a fault-tolerant mapping of rotated surface codes onto a $2\times N$ silicon spin-qubit railway architecture, utilizing electron shuttling to resolve the wiring fan-out bottleneck. Employing circuit-level noise modeling, we evaluate threshold performances across various noise biases. We demonstrate that shuttling check qubits instead of data qubits fundamentally improves system thresholds. Crucially, under a noise model biased towards dephasing for spin-qubit shuttling, the non-CSS XZZX surface code outperforms standard CSS variants. By tailoring the topological code to this specific inherent bias, we show that the Megaquop footprint is achievable with a distance 7 code requiring a $p = 10^{-3}$ physical error rate, highlighting a pathway for substantial hardware reductions in early fault-tolerant quantum processors.