Si/SiGe multi-channel superlattice structure epitaxial growth with segmented temperature control for Next-Generation Logic Devices

TL;DR

This paper presents a novel epitaxial growth process for Si/SiGe multi-channel superlattices with segmented temperature control, reducing interdiffusion and strain relaxation for next-generation logic devices.

Contribution

It introduces a process-physics approach to suppress Ge interdiffusion during high-temperature growth, enabling high-quality multi-channel superlattices.

Findings

Reduced Ge diffusion coefficient to 5.6-7% at 650°C

Achieved sharp interfaces with 1.5-2.6 nm transition width

Maintained design targets in top stack despite prolonged high-temperature exposure

Abstract

Stacking multiple SiSiGe channels in advanced logic devices faces severe thermal budget accumulation, which degrades interfaces via Ge-Si interdiffusion and strain relaxation.This strategy lowers the Ge diffusion coefficient to 5.6-7% of its value at 650C (Arrhenius estimate), suppressing interdiffusion and preserving pseudomorphic strain. The 4 + 4 channel stack exhibits clear XRD satellite peaks, fully coherent strain state (reciprocal space mapping), sharp interfaces (1.5-2.6 nm transition width) and low RMS roughness (0.08 nm). Quantitative analysis from bottom to top reveals that prolonged high-temperature exposure broadens bottom interfaces and dilutes Ge concentration (from 20% to 18.5%), while the top stack maintains design targets. This work provides a process-physics understanding of thermal budget effects in multi-channel superlattices and establishes a high-quality material foundation for advanced logic devices beyond 2 nm node.