An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion

TL;DR

This paper introduces the first fully automated flow for converting single-phase, edge-triggered clocking to two-phase, non-overlapping clocking in digital designs, enhancing timing margin and power efficiency.

Contribution

It presents an integrated, automated methodology within OpenROAD for RTL-to-GDS conversion that manages two-phase clocking, including clock gating and recirculation mux variants.

Findings

Clock-gated variant reduces power by 29.2% and latch count by 50%.

Both variants achieve timing closure via time borrowing.

The flow successfully converts designs that fail timing with flip-flops.

Abstract

Two-phase clocking offers significant advantages in timing margin and clock flexibility, yet its adoption remains limited due to the absence of automation in modern design flows. Managing strict non-overlap and 180$^\circ$ phase separation introduces complexity in RTL implementation and timing closure, leaving two-phase clocking rare in practice. This paper presents the first fully automated two-phase clocking flow integrated into OpenROAD Flow Scripts (ORFS). Our methodology automatically transforms flip-flop-based RTL into two-phase latch-based designs using Yosys technology mapping, ABC retiming, dual clock tree synthesis, two-phase correctness validation, and full physical design from RTL-to-GDS. We implement clock-gated and recirculation mux variants, where clock-gated achieves an average 29.2\% power reduction and 50\% latch count reduction over recirculation mux. Both variants are compared against flip-flop baselines, demonstrating timing closure through time borrowing on a design that failed timing with flip-flops.