Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip

TL;DR

This paper introduces a novel low-power circuit-switched Network-on-Chip design using Spatial Division Multiplexing, significantly reducing power, area, and latency compared to traditional packet-switched NoCs.

Contribution

It proposes a new SDM-based circuit-switched NoC architecture with a specialized router and task mapping algorithm for power-efficient inter-core communication.

Findings

38% lower NoC power consumption compared to conventional designs

19% smaller area than traditional packet-switched NoCs

12% reduction in packet latency

Abstract

In many modern AI chips and multicore systems-on-chip, embedded applications exhibit predictable inter-core traffic behavior that can be characterized at design time. For such applications, a variety of design-time traffic management and network optimization techniques can be employed to improve NoC power and performance. To exploit this predictability, we propose a novel low-power circuit-switched NoC design. It uses the Spatial Division Multiplexing (SDM) technique to establish circuits, implemented as subsets of NoC wires, for the communication flows of a target application. To further reduce the power profile of SDM, the design incorporates a new router architecture that combines hard-wired switches with conventional programmable crossbars. The architecture is complemented by an algorithm that maps application tasks onto a mesh NoC and assigns an SDM route with adequate bit-width to each circuit built for inter-task communication flows. Compared with a conventional packet-switched NoC, the proposed approach achieves approximately 38% lower NoC power consumption, 19% smaller area, and 12% lower packet latency.