Hardware-Aware Neural Feature Extraction for Resource-Constrained Devices

TL;DR

This paper presents Gideon, a neural feature extractor optimized for resource-limited devices, combining neural architecture search and knowledge distillation to achieve high efficiency and robustness under strict hardware constraints.

Contribution

Gideon is a novel hardware-aware neural feature extractor that integrates differentiable architecture search and quantization-aware design for embedded visual SLAM systems.

Findings

Gideon achieves 111 fps inference on STM32N6 with under 1.5 MB memory.

INT8 quantization causes negligible performance loss, sometimes matching full-precision.

Replacing Batch Normalization with affine layers improves INT8 robustness.

Abstract

Visual SLAM is a core component of spatial computing systems, yet deploying learned local feature extractors on microcontroller-class hardware remains challenging due to memory, bandwidth, and quantization constraints. While modern neural descriptors provide strong robustness, their practical adoption is often hindered by system-level bottlenecks that are not captured by FLOP-based efficiency metrics. In this work, we introduce Gideon, a hardware-aware neural feature extractor explicitly designed for resource-constrained devices. Our approach combines relational knowledge distillation from a SuperPoint teacher with differentiable neural architecture search (DNAS) under strict memory and operator constraints. Unlike conventional design pipelines, we treat quantization stability and dynamic-range compactness as first-class objectives. We show that architectural choices such as replacing Batch Normalization with affine layers significantly improve INT8 robustness, and that descriptor dimensionality directly governs quantization resilience. Deployed on STM32N6, Gideon achieves 9.003 ms inference time (111 fps) while remaining below a 1.5 MB memory footprint. Remarkably, INT8 quantization induces negligible degradation and occasionally matches full-precision performance. These results demonstrate that robust learned feature extraction can be reconciled with embedded hardware constraints through holistic hardware-algorithm co-design.