Resource Utilization of Differentiable Logic Gate Networks Deployed on FPGAs

TL;DR

This paper analyzes how varying the depth and width of differentiable Logic Gate Networks affects FPGA resource utilization, power, speed, and accuracy, providing insights for optimized on-edge ML deployment.

Contribution

It characterizes the trade-offs between LGN parameters and hardware synthesis metrics on FPGAs, highlighting the importance of the final layer in resource and timing optimization.

Findings

Final layer of LGN significantly impacts resource and timing efficiency.

Deeper and wider LGNs are feasible with a narrow final layer under constraints.

Tradeoff analysis aids ML engineers in selecting optimal LGN architectures for FPGAs.

Abstract

On-edge machine learning (ML) often strives to maximize the intelligence of small models while miniaturizing the circuit size and power needed to perform inference. Meeting these needs, differentiable Logic Gate Networks (LGN) have demonstrated nanosecond-scale prediction speeds while reducing the required resources as compares to traditional binary neural networks. Despite these benefits, the trade-offs between LGN parameters and resulting hardware synthesis characteristics are not well characterized. This paper therefore studies the tradeoffs between power, resource utilization, inference speed, and model accuracy when varying the depth and width of LGNs synthesized for Field Programmable Gate Arrays (FPGA). Results reveal that the final layer of an LGN is critical to minimize timing and resource usage (i.e. 28\% decrease), as this layer dictates the logic size of summing operations. Subject to timing and routing constraints, deeper and wider LGNs can be synthesized for FPGA when the final layer is narrow. Further tradeoffs are presented to help ML engineers select baseline LGN architectures for FPGAs with a set number of Look Up Tables (LUT).