Mitigating Classical Resource Costs in Quantum Error Correction via Generalized qLDPC Predecoding

TL;DR

This paper presents an automated framework for generating predecoders for arbitrary qLDPC codes, significantly reducing decoding resource usage and latency in quantum error correction architectures.

Contribution

It introduces a novel automated predecoder generation method for general qLDPC codes, enabling scalable, efficient quantum error correction hardware implementations.

Findings

Predecoders process over 90% of decoding workload.

Decoder utilization reduced by up to 3,963x.

Supports decoding of approximately 1,200 logical qubits on FPGA.

Abstract

Quantum-classical interfaces (QCIs) for fault-tolerant quantum computing must manage simultaneous, real-time decoding across thousands to millions of logical qubits. Scaling these architectures necessitates sharing expensive decoding resources among logical qubits, which introduces severe resource contention within the QCI. While resolving these bottlenecks through efficient resource distribution remains a persistent challenge, lightweight predecoding holds promise to alleviate strain on shared decoding components by decreasing average latency and decoder usage. Notably, research into both decoder allocation and predecoding has been strictly confined to the surface code. With the growing emphasis on general quantum low-density parity-check (qLDPC) codes, slower decoding speeds will intensify resource contention, while the inherent complexity of these codes will render manual predecoder design unfeasible. To address this gap, we introduce an automated framework designed to generate predecoders for arbitrary qLDPC codes. These automatically constructed predecoders autonomously process over 90% of the decoding workload, cutting overall decoder utilization by up to 3,963x. This includes a reduction of up to 72.71% in computationally demanding ordered statistics decoding (OSD). Furthermore, we detail a highly efficient, pipelined hardware design that allows for the concurrent decoding of approximately 1,200 bivariate bicycle (BB) code logical qubits using a single FPGA. When implemented as a cryogenic ASIC, the architecture scales to support between 36,000 and 360,000 BB code logical qubits, operating within a 1.5 W power limit at 4 K.