Exchange-Only Silicon Based Spin Qubits: Charge Noise, PINN Optimised Pulse Sequences,and Gate-Level Fidelity

TL;DR

This paper introduces a two-stage PINN framework for optimizing pulse sequences in silicon-based exchange-only spin qubits, significantly improving gate fidelity and reducing pulse durations under charge noise.

Contribution

The novel two-stage PINN approach enhances gate fidelity and shortens pulse times for exchange-only spin qubits in silicon, addressing charge noise effects.

Findings

Single-qubit gates achieve >0.99 fidelity within 100 iterations across noise levels.

Stage II reduces pulse durations by 20-40% at all noise levels.

Two-qubit CX gate pulse duration decreases from 31 ns to approximately 22 ns at 1% noise.

Abstract

Exchange-only (EO) spin qubits in silicon realise all-electrical qubit control through pairwise Heisenberg exchange interactions, making them attractive for scalable quantum computation. Their principal vulnerability is charge noise, which couples multiplicatively to the exchange coupling and degrades gate fidelity. We present a \emph{two-stage} Physics-Informed Neural Network (PINN) framework for per-gate pulse optimisation. In \textbf{Stage~I} (iterations~1--100) the PINN maximises the noise-averaged gate fidelity toward a threshold of $\Fth=0.99$; the pulse duration is held fixed at its nominal hardware value. Once the threshold is crossed, \textbf{Stage~II} (iterations~101--250) progressively compresses the total pulse time while maintaining $F\geq\Fth$ via continuous fine-tuning of the pulse-shape parameters. The cost function is a Monte-Carlo ensemble mean-squared error (MSE) averaged over $N_{\rm real}=2000$ quasi-static Gaussian noise realisations drawn fresh at every iteration. We benchmark the framework on the single-qubit gate set $\{X,Y,Z,H\}$ and the two-qubit set $\{X,Y,Z,H,\mathrm{CX}\}$ at noise levels $\sigmaJ/J\in\{1\%,5\%,10\%\}$. All single-qubit gates cross $\Fth$ within the first 100 iterations across all noise levels; Stage~II then reduces pulse durations by 20--40\% from their nominal values. The two-qubit gates follow the same two-phase behaviour, with the CX gate compressing from its nominal \SI{31}{\nano\second} to $\approx\SI{22}{\nano\second}$ at 1\% noise.