A Scalable FPGA Architecture for Real-Time Decoding of Quantum LDPC Codes Using GARI

TL;DR

This paper presents a scalable FPGA architecture for real-time decoding of quantum LDPC codes using the GARI method, optimizing resource use and power efficiency while maintaining low latency.

Contribution

It introduces a flexible, resource-efficient FPGA decoder architecture for quantum LDPC codes based on GARI, capable of scaling and handling correlated errors.

Findings

Achieved 596 ns decoding latency on FPGA for a [[144,12,12]] code.

Reduced resource usage by six times compared to previous GARI-based implementations.

First FPGA implementation of multiple decoders for correlated quantum errors.

Abstract

In this work, we introduce a new hardware architecture for decoding correlated errors in quantum LDPC codes. The decoder is based on message passing and exploits the structure of the detector error model obtained through the recently introduced Graph Augmentation and Rewiring for Inference (GARI) method. The proposed architecture enables flexible scaling and can, in principle, adapt to any quantum LDPC codes using the GARI framework. It leverages resource reuse while maintaining a modest degree of parallelism, thereby reducing power consumption and area requirements, while preserving low decoding latency. As a case study, the architecture was implemented on a VCU19P FPGA as an ensemble of three decoder cores targeting the [[144,12,12]] bivariate bicycle code, achieving an average latency of 596 ns per decoding round. This implementation consumes six times fewer resources than the previous GARI-based proposal, being the first reported implementation of multiple decoder cores for correlated errors on a single FPGA device. This enables better energy-conscious scaling of the quantum error correction layer on the classical side, reducing overall power consumption while meeting real-time constraints without compromising decoding accuracy under correlated errors.