NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures
Muhammad Ihsan Al Hafiz, Artur Podobas

TL;DR
NeuroRing is a scalable FPGA-based SNN accelerator that uses a ring topology and stream-dataflow architecture, enabling efficient large-scale neural network simulations with real-time performance.
Contribution
It introduces a modular, multi-FPGA compatible SNN accelerator with a novel ring topology and stream-dataflow design, supporting existing workflows and demonstrating scalable, energy-efficient performance.
Findings
Achieves faster-than-real-time execution of cortical microcircuit models
Supports modular deployment across multiple FPGAs with good scalability
Provides competitive energy efficiency on FPGA platforms
Abstract
Spiking neural networks (SNNs) are a promising paradigm for energy-efficient event-driven computation, but large-scale SNN execution remains challenging because sparse spike communication and synchronization can dominate runtime. Existing solutions across CPU, GPU, ASIC, and FPGA platforms offer different trade-offs between programmability, efficiency, and scalability. To address this gap, we present NeuroRing, a modular and scalable SNN accelerator based on a stream-dataflow architecture and a bidirectional ring topology, implemented in High-Level Synthesis (HLS) on programmable FPGAs. NeuroRing supports modular single- and multi-FPGA deployment and is compatible with existing SNN workflows through integration with the NEST simulator. We evaluate NeuroRing on the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. Results show that NeuroRing preserves the key…
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