Neuronal arithmetic operators based on Ovonic threshold switches (OTS) for biologically inspired analog computing

TL;DR

This paper introduces OTS-based artificial neurons capable of performing addition, parallel operations, and division, mimicking biological neural computations for efficient, scalable analog computing.

Contribution

It demonstrates novel OTS-based neuron circuits that physically implement arithmetic operations, including divisive gain modulation, with improved energy efficiency and scalability.

Findings

OTS neurons perform addition, parallel, and division operations.

Division neuron achieves Hill-type normalization with R2 ~ 0.95.

Application to image normalization shows practical utility.

Abstract

Biological neurons perform arithmetic computations - including additive integration and divisive gain modulation - through synaptic conductance changes and shunting inhibition, enabling context-dependent information processing that far exceeds simple threshold-and-fire models. Replicating these capabilities in compact hardware remains a fundamental challenge for neuromorphic engineering. Here, we demonstrate artificial neuron circuits based on Ovonic threshold switches (OTS) that physically implement three arithmetic operations: SUM, PARALLEL, and DIVISION. The SUM and PARALLEL neurons exploit MOSFET-controlled dendritic conductances, producing output firing rates that collapse onto invariant curves as a function of combined inputs - satisfying the canonical criteria for neuronal addition. The DIVISION neuron leverages a JFET-based shunting pathway, inspired by GABA_A-mediated inhibition in the cortex, to achieve divisive gain modulation well described by a Hill-type function (R2 ~ 0.95, Hill exponent n ~ 1.3), consistent with nonlinear normalization observed in visual and olfactory circuits. Applying the DIVISION neuron to pixel-wise image normalization under non-uniform illumination recovers obscured visual content, mirroring contrast normalization in the visual cortex. Compared to CMOS-based division implementations, the proposed approach offers improvements in energy efficiency and scalability exceeding an order of magnitude, establishing a viable path toward compact, brain-inspired analog computing.