Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL

TL;DR

This paper presents a comprehensive pre-silicon verification and validation methodology for RISC-V chips, integrating multiple platforms and automation to ensure high reliability and system-level correctness.

Contribution

It introduces a holistic V&V approach combining UVM, FPGA validation, and CI/CD pipelines for RISC-V chip development.

Findings

Enables continuous hardware and software validation using large-scale infrastructure.

Provides a scalable, industrial-grade V&V flow for RISC-V designs.

Supports strategic European initiatives in chip development.

Abstract

The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon verification and validation (V&V) methodology targeting highly robust RISC-V chip designs. This paper provides an overview of BZL's V&V approach, which integrates three complementary platforms: (1) a UVM-based verification environment to thoroughly validate RTL functionality; (2) an FPGA-based validation platform that enables system-level pre-silicon hardware-software RTL validation; and (3) a CI/CD flow that continuously automates build, deployment, and tests across these domains. By embedding these platforms into an industrial-grade V&V loop and exploiting large-scale CPU and FPGA hardware infrastructures, the BZL project enables continuous evolution of reliable hardware development and software integration. We believe that the BZL's V&V flow represents a robust and scalable foundation for ensuring the pre-silicon functional correctness and system level validation of RISC-V chip designs, and can serve as a key enabler for strategic initiatives in Europe, such as EPI and DARE, and beyond.