EMiX: Emulating Beyond Single-FPGA Limits

TL;DR

EMiX is a scalable multi-FPGA framework that partitions and distributes large multi-core RISC-V system emulations across interconnected FPGAs, enabling full-system validation beyond single-FPGA limits.

Contribution

It introduces a systematic partitioning approach and a multi-FPGA framework for large-scale emulation without needing RTL redesign.

Findings

Successfully emulated a 64-core system across eight FPGAs.

Demonstrated Linux boot on a multi-core system.

Scalable on core and FPGA counts.

Abstract

FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system emulation. To address this challenge, we introduce EMiX, a scalable multi-FPGA framework that enables distributed emulation of multi-core RISC-V architectures beyond single-FPGA resource limits. EMiX systematically partitions a monolithic multi-core design into multiple components and deploys them across multiple interconnected FPGAs, effectively exploiting inter-FPGA interconnects to balance scalability and performance without requiring fundamental RTL redesign. We prototype EMiX with a 64-core architecture across eight interconnected Alveo U55c FPGAs (scalable on core and FPGA counts), successfully demonstrating full-system execution including Linux boot. EMiX will be released as an open-source platform.