System-Level Design of Scalable Fluxonium Quantum Processors with Double-Transmon Couplers

TL;DR

This paper presents a comprehensive design framework for scalable fluxonium quantum processors using double-transmon couplers, optimizing spectral allocation and device parameters for high performance.

Contribution

It introduces a frequency-partitioned architecture and multi-objective optimization approach for fluxonium processors with DTCs, enabling scalable, high-fidelity quantum operations.

Findings

Feasible parameter regimes for high-fidelity gates identified

Structured spectral allocation reduces parameter interdependence

Workflow supports scalable, robust quantum processor design

Abstract

Fluxonium qubits combine long coherence times with strong anharmonicity, making them a promising platform for scalable superconducting quantum processors. Recent experiments have demonstrated high-fidelity operations in multi-qubit processors while suppressing stray qubit interactions using fluxonium-transmon-fluxonium (FTF) architectures. However, scaling such systems to larger arrays is constrained by a trade-off between achievable coupling strength, crosstalk suppression and qubit-qubit spacing required for wiring in a two-dimensional architecture. Multimode couplers, such as the double-transmon coupler (DTC), provide a promising pathway to overcome this limitation by enabling stronger interactions without compromising qubit spacing and isolation. Here, we develop a quantitative design framework for fluxonium-based quantum processors employing DTCs. Central to this work is a frequency-partitioned architecture that places qubit transitions, tunable-coupler excitations, and resonator modes in well-separated spectral regions. This structured allocation reduces parameter interdependence and enables the concurrent optimization of gate operations, readout, and qubit reset. By formulating device design as a multi-objective optimization problem under realistic experimental constraints and fabrication-induced disorder, we develop a tractable sequential workflow and determine a feasible parameter regime that simultaneously supports high-fidelity single- and two-qubit gates, fast qubit reset, and robust dispersive readout. These results establish a system-level architectural methodology that links circuit parameters to processor-level performance, and provide an experimentally actionable pathway toward scalable fluxonium quantum processors.