CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling

TL;DR

This paper presents a novel approach for implementing quantum low-density parity check codes on a tileable spin qubit chip, optimizing shuttle scheduling and syndrome extraction to enhance scalability and error correction.

Contribution

It introduces a tailored shuttle scheduling algorithm and circuit-level optimizations that significantly improve the feasibility and performance of QLDPC codes on shuttling-based spin qubit architectures.

Findings

Shuttling range extended by 5-10x enabling complex code implementation.

Optimized schedules are up to 86% faster than hand-optimized ones.

Certain QLDPC codes outperform prior surface code implementations by orders of magnitude.

Abstract

Semiconductor spin qubits are a promising platform for large-scale quantum computing, but have yet to take full advantage of the broad class of quantum low-density parity check (QLDPC) codes, which promise high encoding rates and efficient logic but require nonlocal connectivity between physical qubits. In this work, we investigate the implementation of QLDPC codes on a tileable, shuttling-based spin qubit architecture. By tailoring syndrome extraction circuits to the shuttling noise model, we significantly improve on previous surface code proposals and extend the feasible shuttling range of the architecture by 5-10x, enabling the implementation of more complex codes with long-range interactions. Taking inspiration from the field of robotics, we develop a coordinated shuttle scheduling algorithm that supports arbitrary codes and use it to benchmark the logical performance of a variety of promising code families. We find that the optimized schedules are up to 86% faster than hand-optimized schedules for certain code families. Through detailed circuit-level simulations, we identify specific QLDPC codes that improve upon prior surface code implementations by orders of magnitude, increasing encoding efficiency and reducing logical error rates. This work demonstrates the potential of shuttling-based spin qubit hardware platforms for scalable and efficient fault-tolerant quantum computation.