D\'ej\`a Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization
Milo Liebster, Amin Mohaghegh, Andrew Boutros

TL;DR
This paper introduces D'ejà Vu packing, a method that significantly accelerates FPGA logic clustering by memoizing recurring pattern legality checks, reducing overall CAD flow runtime.
Contribution
It proposes a novel packing signature tree data structure to identify and reuse packing legality outcomes, improving FPGA clustering efficiency.
Findings
Speeds up packing by up to 29.3x on average.
Reduces end-to-end VPR runtime by up to 5.3x.
Maintains quality of results despite runtime improvements.
Abstract
Implementing a digital circuit on an FPGA fabric requires clustering technology-mapped netlist primitives into coarser-granularity blocks that can be directly mapped to the physical resources available on the FPGA. As the architecture of FPGA logic blocks (LBs) has grown in complexity, with sophisticated logic elements (LEs) and highly irregular local interconnect, this packing problem has become more challenging. To ensure the feasibility of intracluster routing, the computer-aided design (CAD) tools must solve a costly multi-source multi-sink routing problem for each candidate cluster. In this paper, we first show that such packing legality checks consume a significant portion of the CAD flow runtime for LB architectures with complex LEs and local routing structures resembling modern commercial FPGAs. We demonstrate that the packing stage constitutes 58% and 94% of the entire…
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