A Multiplication-Free Spike-Time Learning Algorithm and its Efficient FPGA Implementation for On-Chip SNN Training

TL;DR

This paper introduces a multiplication-free, spike-time-based learning algorithm for SNNs, optimized for FPGA implementation, enabling efficient, real-time on-chip training with high accuracy and low resource consumption.

Contribution

The paper presents a novel, fully event-driven, multiplication-free learning algorithm tailored for FPGA hardware, improving efficiency and scalability of on-chip SNN training.

Findings

Achieved 96.5% accuracy on MNIST

Implemented on Xilinx Artix-7 FPGA with minimal resources

Validated scalability with Fashion-MNIST

Abstract

Spiking Neural Networks (SNNs) offer a biologically inspired foundation for low-power, event-driven intelligence, yet their direct on-chip supervised training remains a key hardware challenge. This paper presents a multiplication-free, spike-time-based learning algorithm specifically designed for efficient FPGA realization. The proposed approach eliminates floating-point arithmetic and explicit gradient storage, enabling a fully event-driven, digital training pipeline. Implemented on a Xilinx Artix-7 FPGA, the architecture achieves high operating speed and minimal resource usage while maintaining competitive accuracy. These results demonstrate that the learning algorithm effectively maps onto reconfigurable hardware, achieving both computational and energy efficiency. Software simulations further validate scalability, with 96.5\% and 84.8\% accuracy on MNIST and Fashion-MNIST. With its spike-driven and multiplier-free operation, the proposed framework delivers a practical and scalable hardware solution for real-time, on-chip SNN learning in edge environments.