Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures

TL;DR

This paper introduces an in-memory stochastic computing architecture using MTJ-based memory with logic-in-memory capabilities to enhance parallelism and reduce data movement in high-performance systems.

Contribution

It presents a novel integrated stochastic computing architecture within MTJ memory, enabling fully parallel probabilistic processing without external random number generators.

Findings

Enables fully parallel conversion of binary to probabilistic bit-streams.

Reduces hardware complexity and energy consumption compared to traditional methods.

Maximizes memory-level parallelism by integrating storage and computation.

Abstract

Today's high-performance architectures are increasingly constrained by data movement latency and energy overhead, as the slowdown of single-core performance scaling coincides with the rise of highly data-intensive workloads. In-memory architectures have emerged as a complementary solution to conventional von Neumann systems by alleviating memory bandwidth bottlenecks, exploiting massive concurrency, and mitigating excessive data movement between memory and processing units. This study proposes a parallel in-memory stochastic computing (SC) architecture that implements an end-to-end computation pipeline within Magnetic Tunnel Junction (MTJ)-based memory augmented with logic-in-memory (LIM) capabilities. By leveraging the inherent stochasticity and write-read characteristics of MTJ devices, the proposed architecture enables a fully parallel and deterministic conversion of binary operands into probabilistic bit-streams, eliminating the need for energy-intensive external random number generation circuitry. These bit-streams are processed by parallel stochastic arithmetic units integrated directly within the memory arrays to efficiently implement core arithmetic and transcendental functions with minimal hardware complexity and inherent noise tolerance. The resulting stochastic outputs can be either reused as an input of future stochastic processing or converted back to binary form using parallel accumulation mechanisms and stored in the MTJ memory. By tightly integrating data storage, bit-stream generation, and computation within a unified in-memory fabric, the proposed design maximizes memory-level parallelism while substantially minimizing data movement.