Pulse Shaping to Mitigate the Impact of Device Imperfections in Field-Free Switching Using Combined Spin-Orbit and Spin-Transfer Torques

TL;DR

This paper explores pulse shaping techniques to reduce write error rates in SOT-MRAM devices combining spin-orbit and spin-transfer torques, addressing reliability issues caused by device imperfections.

Contribution

It introduces a macrospin model for combined SOT + STT switching, revealing asymmetries and loss-of-determinism, and demonstrates pulse shaping as an effective mitigation strategy.

Findings

STT pulse shaping reduces write error rate

Backhopping phenomena are observed and mitigated

Asymmetry between AP-to-P and P-to-AP switching is characterized

Abstract

Combining spin-orbit (SOT) and spin-transfer torques (STT) provides a practical approach for field-free switching in spin-orbit torque magnetic random-access memory (SOT-MRAM), a prerequisite for industrial deployment, but can compromise reliability through phenomena such as backhopping, especially in top-pinned stacks commonly used for SOT-MRAM. We investigate the write error rate (WER) of combined SOT + STT switching in top-pinned devices that are not optimized for STT switching. Experiments reveal clear indications of STT-induced backhopping and a pronounced field-free SOT switching asymmetry between AP-to-P and P-to-AP transitions. Our macrospin model, using two coupled Landau Lifshitz Gilbert equations for the free and the reference layers, qualitatively reproduces this asymmetry and reveals an intermediate loss-of-determinism regime in addition to the well-known backhopping region. Based on these simulations, we propose mitigation strategies and experimentally demonstrate that STT pulse shaping reduces WER and improves switching robustness in the presence of device imperfections.