Hardware-Software Co-Design for Event-Driven SNN Deployment on Low-Cost Neuromorphic FPGAs

TL;DR

This paper introduces a hardware-software co-design framework enabling the deployment of PyTorch-defined SNNs on low-cost FPGA hardware, ensuring reproducibility and efficiency in neuromorphic computing.

Contribution

It presents a unified artifact for SNN deployment that preserves semantics and bridges software and hardware, facilitating practical FPGA-based neuromorphic systems.

Findings

Achieved 87.40% accuracy on MNIST TTFS classifier

Delivered a latency of 0.1375 μs/image on FPGA

Estimated dynamic energy consumption of 31.6 nJ/image

Abstract

Low-cost FPGA platforms can broaden access to neuromorphic systems research, but current spiking neural network (SNN) workflows remain divided between hardware-first implementations, which are difficult to integrate with PyTorch-style development, and software-first frameworks, which often stop at simulation or GPU execution. This paper presents a semantics-preserving hardware-software co-design framework for the deterministic deployment of PyTorch-defined SNNs to event-driven FPGA execution. A single exported artifact carries weights, thresholds, connectivity descriptors, and grouped time-to-first-spike (TTFS) decoding metadata from software definition to board execution and is reused unchanged by both the software reference and the board runtime. A 10-class MNIST TTFS classifier implemented in the routed 80 MHz design achieves 87.40\% accuracy and matches the software reference on all 10,000 test images. The programmable-logic path delivers a service latency of 0.1375 {\mu}s/image and an estimated dynamic energy of 31.6 nJ/image, while scope-aware comparisons with matched GPU and CPU baselines keep accelerator-only and system-level measurements distinct. These results show that low-cost event-driven FPGA hardware can provide a direct and reproducible software-to-board path for software-defined SNN models.