SPAC: Automating FPGA-based Network Switches with Protocol Adaptive Customization
Guoyu Li, Yang Cao, Lucas H L Ng, Alexander Charlton, Qianzhou Wang, Will Punter, Philippos Papaphilippou, Ce Guo, Hongxiang Fan, Wayne Luk, Saman Amarasinghe, Ajay Brahmakshatriya

TL;DR
SPAC automates the design of FPGA-based network switches tailored to specific protocols and traffic patterns, optimizing performance and resource usage for diverse applications.
Contribution
It introduces a unified workflow with a DSL, adaptive components, and a trace-aware DSE engine for automated, protocol-aware FPGA switch customization.
Findings
SPAC reduces LUT and BRAM usage by over 50%.
Latency improvements of up to 38.4% are achieved.
Designs are effective across diverse real-world scenarios.
Abstract
With network requirements diverging across emerging applications, latency-critical services demand minimal logic delay, while hyperscale training and collectives require sustained line-rate throughput for synchronized bulk transfers. This divergence creates an urgent need for custom network switches tailored to specialized protocols and application-specific traffic patterns. This paper presents SPAC (Switch and Protocol Adaptive Customization), a novel approach that automates the generation of FPGA-based network switches co-optimized for custom protocols and application-specific traffic patterns. SPAC introduces a unified workflow with a domain-specific language (DSL) for protocol-architecture co-design, a library of modular HLS-based adaptive switch components, and a trace-aware Design Space Exploration (DSE) engine. By providing a multi-fidelity simulation stack, SPAC enables rapid…
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