AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout

TL;DR

AnalogMaster leverages large language models to automate the entire analog IC design process from schematic images to layout, significantly reducing manual effort and improving efficiency.

Contribution

The paper introduces AnalogMaster, a novel LLM-based framework enabling end-to-end analog IC design automation across multiple stages with high success rates.

Findings

GPT-5 achieves 92.9% Pass@1 success rate.

Framework demonstrates strong performance across 15 circuits.

Unified pipeline effectively integrates image-to-netlist, optimization, placement, and routing.

Abstract

Design automation has the potential to substantially improve the efficiency of analog integrated circuit (IC) design. However, existing algorithms and tools typically focus on individual stages, such as device sizing, placement, or routing, and still require significant manual intervention to complete the full design flow. While large language models (LLMs) have recently demonstrated remarkable success in automating digital IC design workflows, these advances cannot be directly transferred to analog IC design. Key challenges include strongly coupled performance metrics, the predominance of unstructured circuit schematic images, and the fact that most prior approaches address only isolated stages of the analog design process, limiting their ability to capture end-to-end performance impact. To address these challenges, we propose AnalogMaster, an extensible, LLM-based framework that enables end-to-end automation of analog IC design through a unified pipeline spanning circuit image-to-netlist generation, parameter optimization, placement, and routing. AnalogMaster integrates a joint reasoning mechanism that leverages in-context learning and intent reasoning to achieve accurate and robust image-to-netlist conversion. A parameter search agent integrating self-enhanced prompt engineering and context truncation is developed for effective device sizing and downstream physical design. Experimental evaluations on 15 representative circuits with varying levels of complexity demonstrate strong and consistent performance across multiple models. In particular, GPT-5 achieves success rates of 92.9% and 99.9% on Pass@1 and Pass@5, respectively. These results validate the effectiveness and robustness of the proposed framework and establish a practical paradigm for applying LLMs to full-stack analog IC design automation.