Valley-Aware Optimal Control of Spin Shuttling Using Cryogenic Integrated Electronics

TL;DR

This paper presents a cryogenic control system for spin qubit electron shuttling that enhances fidelity and scalability by integrating waveform generation, valley disorder mitigation, and noise-aware optimization.

Contribution

It introduces a co-simulation framework, an integrated cryogenic shuttling signal generator, and a noise-aware optimization method for high-fidelity spin shuttling.

Findings

Achieves 99.99% shuttling fidelity over 10 μm at 20 m/s.

Maintains active power consumption in the tens of μW range.

Validates on-chip storage and replay of control settings for disorder mitigation.

Abstract

Electron shuttling is emerging as a key mechanism for enabling long-range coupling in scalable spin-qubit architectures. Bringing shuttling waveform generation into the cryostat can improve scalability, but imposes strict area and power constraints on the control electronics. Concurrently, shuttling in Si/SiGe is further limited by a spatially varying valley splitting that induces spin--valley mixing and degrades coherence. Here, we make three contributions that address these limitations jointly: (i) an end-to-end co-simulation framework that combines disorder-informed valley maps with transistor-level cryogenic circuit simulations including electronic noise; (ii) a fully integrated cryogenic shuttling-signal generator tailored to velocity modulation, enabling period-wise waveform shaping through discrete circuit settings stored in on-chip memory; and (iii) a noise-aware optimization procedure that tunes only these implementable circuit controls, using one of four discrete resistor settings per period, to generate high-fidelity shuttling sequences. Across simulated valley and noise realizations in our co-simulation framework, the optimized velocity-modulation waveforms improve transport performance, achieving an average shuttling fidelity of $99.99 \pm 0.007\%$ at $v_{\mathrm{avg}} = 20~\mathrm{m\,s^{-1}}$ over a distance of $10~\mu\mathrm{m}$, while maintaining active analog power consumption in the tens of $\mu\mathrm{W}$ during shuttling. This validates on-chip storage and replay of optimized control settings as a practical strategy to mitigate valley disorder in scalable shuttling architectures.