Design Space Exploration for ReRAM-based Architectures to Address Scaling Non-idealities

TL;DR

This paper introduces a framework for efficiently exploring design options in ReRAM-based in-memory computing architectures, optimizing for energy efficiency while managing scaling challenges.

Contribution

It presents a novel, parameter-based exploration method that reduces reliance on exhaustive simulations for designing scalable ReRAM IMC systems.

Findings

Framework accurately predicts performance of various architectures.

Successfully identifies optimal configurations under power and error constraints.

Enhances design efficiency for high-performance ReRAM IMC systems.

Abstract

ReRAM-based in-memory computing (IMC) architectures are promising candidates for energy-efficient matrix-vector multiplication. While scaling the size of ReRAM arrays allows for the amortization of power-hungry peripheral circuits like DACs and ADCs, it simultaneously introduces more parasitic along the signal path. Because of these challenges, current design methodologies often lack practical guidelines to balance these effects at early design stage, forcing designers to rely on time-consuming, iterative transistor-level simulations. In this work, we propose a comprehensive framework for design space exploration that enables the selection of optimal array size, ADC resolution, and system frequency without requiring exhaustive simulations. The framework utilizes a specialized testbench to extract parameters from a limited set of representative transistor-level simulations. These parameters are then used to accurately predict the performance of arbitrary architectures. We demonstrate the effectiveness of this framework through two realistic design cases aimed at maximizing energy efficiency (TOPs/s/W). The results show that the framework successfully identifies optimal architectural configurations under strict power and error constraints, providing an efficient path for high-performance IMC design.